The present invention relates to a variable frequency divider and a PLL circuit, and more particularly to a PLL circuit which generates an output signal frequency consistent with a set frequency.
In recent years, PLL circuits have been used in mobile communication equipments, such as mobile and portable telephones. In such a PLL circuit, the output signal frequency must be switched swiftly into a desired frequency in order to improve usefulness of the mobile communication equipment. Recently, a time-sharing frequency switching system has been adopted to make effective use of the frequency. In such a system, it is especially important that the output signal frequency of the PLL circuit is switched in a fast rate and a short period.
FIG. 1 illustrates a first example of a conventional PLL circuit. A shift register circuit 1 receives serial data SD in accordance with the rise of a clock signal CLK. The shift register circuit 1 then provides, for example, a 10 bits of parallel data for setting a frequency dividing ratio to a latch circuit 2. The latch circuit 2 latches the parallel data in accordance with the rise of a latch signal LE and provides a frequency dividing ratio setting signal DLH to a comparison counter circuit 3. The comparison counter circuit 3 divides the frequency of an input signal IN on the basis of the frequency dividing ratio set by the frequency dividing ratio setting signal DLH, and provides a frequency dividing signal LD to a phase comparator 4, as a comparison signal. At the same time, the comparison counter circuit 3 receives a frequency dividing signal LD, as a load signal.
The phase comparator 4 receives the frequency dividing signal LD and a reference signal REF supplied from a reference frequency divider (not shown). The phase comparator 4 then compares the frequency dividing signal LD and the reference signal REF, and outputs a pulse signal corresponding to the difference in frequency and the difference in phase to a charge pump 5. A pull-up side transistor or pull-down side transistor of the output stage of the charge pump 5 is turned on in accordance with the pulse signal outputted from the phase comparator 4. The charge pump 5 has a loop filter 6 on the subsequent stage as a load, and increases the output voltage as the pull-up side transistor goes on and decreases the output voltage as the pull-down side transistor goes on. The loop filter 6 functions as the load of the charge pump 5, and smooths the output signal of the charge pump 5 to output a smoothed output signal to a voltage controlled oscillator (VCO) 7. The VCO 7 outputs an output signal of a frequency corresponding to an output voltage of the loop filter 6. The output signal is an input to the comparison counter circuit 3.
FIG. 2 is a block diagram of the latch circuit 2 and the comparison counter circuit 3 of FIG. 1. The latch circuit 2 comprises a plurality of D flip flop circuits 8. Each of the flip flop circuits 8 receives the parallel data output from the shift register 1. Each of the flip flop circuits 8 also receives the latch signal LE and latches the parallel data in accordance with the rise of the latch signal LE and output the frequency dividing ratio setting signals DLH.
The comparison counter circuit 3 comprises a plurality of flip flop circuits 9 connected in series. Each of the flip flop circuits 9 receives the signal DLH at its data input, and the first stage flip flop circuit 9 receives the input signal IN at its clock input CK. The signal DLH is latched by each of the flip flop circuits 9 in accordance with the input of the frequency dividing signal LD. Each output signal of the flip flop circuits 9 is input to an AND gate 10, which outputs the frequency dividing signal LD.
The comparison counter circuit 3 counts up the pulse number of input signals IN, using a value set in each of the flip flop circuits 9 by the frequency dividing ratio setting signal DLH as a count start value. When all of the output signals from the flip flop circuits 9 are high, a count-up operation is completed, and the AND gate 10 outputs an H level frequency dividing signal LD having a time length corresponding to one cycle of the input signal IN. When the H level frequency dividing signal LD is input to each of the flip flop circuits 9, the frequency dividing ratio is reset in each of the flip flop circuits 9, and the count-up operation resumes in accordance with the new frequency dividing ratio.
Referring now to FIG. 3, each time the clock signal CLK is input to the shift register 1, the shift register 1 outputs the parallel data. Then, when the latch circuit 2 receives the latch signal LE, the latch circuit 2 latches the parallel data in accordance with the rise of the latch signal LE and outputs the frequency dividing ratio setting signal DLH. Accordingly, the frequency dividing ratio setting signal DLH is switched in accordance with the rise of the latch signal LE. When the comparison counter circuit 3 outputs a frequency dividing signal LD, in accordance with the frequency dividing signal LD, a new frequency dividing ratio setting signal DLH is received by the comparison counter circuit 3, and a new counting operation is initiated.
However, in operation, the clock signal CLK and latch signal LE are asynchronous with the input signal IN of the comparison counter circuit 3. Accordingly, the switching of the frequency dividing ratio setting signal DLH is asynchronous with the frequency dividing signal LD. Accordingly, if the fall of the frequency dividing signal LD overlaps a time t1 required for switching the frequency dividing ratio setting signal DLH, the frequency dividing ratio setting signal DLH received by the comparison counter circuit 3 is not stable. Therefore, a normal frequency dividing ratio is not set in the comparison counter circuit 3, thereby inviting a risk of malfunction.
FIG. 4 illustrates a second example of a conventional PLL circuit which prevents the aforementioned malfunction of the comparison counter circuit. The same parts as those of the first example will be described with the same numerals. A first latch circuit 2a is supplied with the parallel data and the latch signal LE. The first latch circuit 2a latches the parallel data, in accordance with the latch signal LE, and outputs a first frequency dividing ratio setting signal DLH1 to a second latch circuit 2b. The second latch circuit 2b receives the first frequency dividing ratio setting signal DLH1 and a latch signal LEC. The second latch circuit 2b latches the signal DLH1, in accordance with the latch signal LEC, and outputs a second frequency dividing ratio setting signal DLH2 to the comparison counter circuit 3. The comparison counter circuit 3 generates the frequency dividing signal LD, as previously discussed.
The frequency dividing signal LD is provided to a load timing control circuit 11. The load timing control circuit 11 comprises flip flop circuits 12a to 12c and an AND gate 13. The flip flop circuit 12a receives the frequency dividing signal LD as data D and the input signal IN as a clock signal CK. The flip flop circuit 12a then outputs a latched output signal L1 in accordance with the rise of the input signal IN. The flip flop circuit 12b receives the output signal L1 as data D and the input signal IN as a clock signal CK. The flip flop circuit 12b then outputs a latched output signal L2 in accordance with the rise of the input signal IN. The flip flop circuit 12c receives the output signal L1 as a clock signal CK and the latch signal LE as data D. The flip flop circuit 12c then outputs a latched output signal L3 in accordance with the rise of the output signal L1. The AND gate 13 receives the output signals L2, L3 and outputs a latch signal LEC.
The operation of the PLL circuit thus constructed will be described with reference to FIG. 5. When the switching of the first frequency dividing ratio setting signal DLH1 overlaps the falling of the frequency dividing signal LDa, the output signal L3 is kept in the L level depending on the timing of the output signal L1 and the latch signal LE, and the output of the latch signal LECa, based on the frequency dividing signal LDa, is interrupted. As the result, the comparison counter circuit 3 normally receives the frequency dividing ratio setting signal DLH1, which prevents malfunction of the comparison counter circuit 3.
Specifically, when the latch signal LE is input to the first latch circuit 2a, the signal DLH1 switches in accordance with the rise of the latch signal LE. The comparison counter circuit 3 outputs a frequency dividing signal LDa that falls from high to low while the signal DLH1 switches. The frequency dividing signal LDa rises, thereafter the output signal L1a from the flip flop circuit 12a rises in accordance with the rise of the input signal IN. The frequency dividing signal LDa falls, thereafter the output signal L1a falls in accordance with the rise of the input signal IN. Therefore, the output signal L1a is in phase with the signal LDa and has a specific delay time. The delay time is set so that the output signal L1a rises prior to the latch signal LE. When the output signal L1a rises, the latch signal LE is still low. Therefore, the output signal L3 of the flip flop circuit 12c is kept low. When the output signal L1a rises, and thereafter the input signal IN rises, the output signal L2a rises. When the output signal L1 falls, and thereafter the input signal IN rises, the output signal L2 falls. Therefore, the output signal L2 is in phase with the output signal L1 and has a specific delay time.
When the output signal L2 goes high, since the output signal L3 is kept in low, the latch signal LEC is kept low. Accordingly, the second latch circuit 2b does not receive the signal DLH1, and the signal DLH2 does not switch.
When the frequency dividing signal LDb rises, while the latch signal LE is kept high, the output signals L1b, L2b are output with a specific delay time in the same manner as the output signals L1a, L2a. The output signal L3 rises in accordance with the rise of the output signal L1b, when the latch signal LE is kept high. When the output signal L1c rises in accordance with the rise of the next frequency dividing signal LDc, if the latch signal LE is low, the output signal L3 falls. Since the output signal L2b is high while the output signal L3 is low, the AND gate 13 outputs the latch signal LEC in phase with the output signal L2b.
The second latch circuit 2b latches the signal DLH1 in accordance with the latch signal LEC and outputs the second frequency dividing ratio setting signal DLH2. Accordingly, the signal DLH2 is switched. The comparison counter circuit 3 receives the signal DLH2 in accordance with the next frequency dividing signal LDc, and starts to count the input signal IN in accordance with a frequency dividing ratio set by the second frequency dividing ratio setting signal DLH2.
If the latch signal LE rises and thereafter the frequency dividing signal LDb rises, the latch signal LEC is generated, and the signal DLH2 is switched in accordance with the latch signal LEC.
In the second conventional example, when the frequency dividing signal LDb rises while the latch signal LE is high, the latch signal LEC goes high so that the latched second frequency dividing ratio setting signal DLH2 switches.
Then, the comparison counter circuit 3 receives the signal DLH2 in accordance with the rise of the next cycle frequency dividing signal Ldc. The comparison counter circuit 3 receives the signal DLH2 after the first frequency dividing ratio setting signal DLH1 is switched by the latch signal LE, which takes some time for switching the frequency dividing ratio.
When the rising of the latch signal LE and the falling of the frequency dividing signal LDa overlap, the latch signal LECa is masked, and the signal DLH2 is switched in accordance with the next frequency dividing signal LDb. The comparison counter circuit 3 receives the signal DLH2 in accordance with the rise of the next frequency dividing signal Ldc. That is, the signal DLH1 is switched by the latch signal LE and then the signal DLH2 is not received by the comparison counter until the rise of LDc. Therefore, it takes still more time for switching the frequency dividing ratio, and thus, the switching of the output signal frequency in the PLL circuit requires extra time.
Further, in order to generate the latch signal LEC in accordance with the rise of the frequency dividing signal LD after the latch signal LE rises and the first frequency dividing ratio setting signal DLH1 is switched, the latch signal LE necessarily takes a longer time than one cycle of the frequency dividing signal LD. That is, the switching cycle of the first frequency dividing ratio setting signal DLH1 takes a time more than about two cycles of the frequency dividing signal LD. Therefore, the switching cycle of the frequency dividing ratio of the comparison counter circuit 3 requires a time more than about two cycles of the frequency dividing signal LD. Consequently, the switching period of the output signal frequency in the PLL circuit becomes longer.
It is an object of the present invention is to provide a PLL circuit capable of switching the output signal frequency in a fast rate and a short period.